1. Technical Field
Embodiments described herein relate to integrated circuits, and more particularly, to techniques sensing data stored in data storage cells.
2. Description of the Related Art
Memories typically include a number of data storage cells composed of interconnected transistors fabricated on a semiconductor substrate. Such data storage cells may be constructed according to a number of different circuit design styles. For example, the data storage cells may be implemented as a single transistor coupled to a capacitor to form a dynamic storage cell. Alternatively, cross-couple inverters may be employed to form a static storage cell or a floating gate metal-oxide semiconductor field-effect transistor (MOSFET) may be used to create a non-volatile storage cell.
In various memory architectures, groups of data storage cells are arranged in arrays of rows and columns. Each data storage cell within a particular column is coupled to a data line (also referred to herein as a “bit line”). Additionally, each data storage cell within the particular column is coupled to a respective selection signal (also referred to herein as a “word line”).
During a read operation, a particular data storage cell is selected by activating its corresponding selection signal. The selected data storage cell may then generate a small signal on its associated data line. An amplifier (commonly referred to as a “sense amplifier”) is employed to amplify the small signal. In some cases, the amplification process results in a digital signal corresponding to the data stored in the selected data storage cell. Other memory architectures may employ multiple stages of amplification.